There have been great advances in the speed and power of integrated circuits, such as application specific integrated circuit (ASIC) chips, random access memory (RAM) chips, microprocessor (uP) chips, and the like. These advances have made possible large scale integration of complex electronic systems onto only a few integrated circuit chips. In some cases, a complex electrical system (i.e., cell phone, television receiver, or the like) may be integrated onto a single system-on-a-chip (SOC) device. SOC devices greatly reduce the size, cost, and power consumption of the system.
An important consideration of any highly integrated electronic system is power consumption. Minimizing power consumption reduces the cost of operating an electronic component and also reduces the heat dissipation requirements of the device in which the electronic component is disposed.
Buffer circuits (i.e., line drivers) with tristate outputs allow multiple hardware resources (e.g., any generalized processing system) to share a common bus (address or data) in a time-multiplexed fashion. At any instant, one hardware resource has exclusive access to the bus, while other resources await their turn to gain access to the bus. Requests for the bus from hardware resources are sent to an arbitrator, which resolves these requests, and grants exclusive access to one resource. The hardware resources send bus access requests to a bus arbitrator circuit. The arbitrator resolves these requests and grants exclusive access to one resource by means of enable signals. These enable signals establish a connection between the bus and the requesting resource by means of tri-state buffer circuits.
Dynamic power dissipation in the tristate buffers consists of two components:
1) Load power—If a large number of hardware resources share the bus, it presents a large load capacitance to the tristate buffers/line drivers. Electrical power is dissipated in the tristate line drivers when this load capacitance is charged and discharged.
2) Short circuit power—Ideally, when a tristate driver connected to a hardware resource is turned ON, all of the tristate line drivers connected to the other hardware resources on the shared bus are turned OFF to avoid a short-circuit current through the drivers. In practice, however, this does not happen due to unequal delays in the bus arbitrator circuit. The resulting short-circuit currents are significant, because the tristate drivers are designed to supply large currents to quickly charge or discharge the bus capacitance.
FIG. 2 illustrates bus arbitrator 210 and tristate line drivers 230A and 230B associated with shared data bus 240 according to an exemplary embodiment of the prior art. FIG. 3 is a timing diagram illustrating the operation of bus arbitrator 210 and tristate line driver 230A and 230B in FIG. 2. In the illustrated embodiment, bus arbitrator 210 provides enable signals EN1 and EN2 to tristate line drivers 230A and 230B, respectively. Tristate line drivers 230A and 230B are connected to Data Bit Line 1 of exemplary shared data bus 240. Arbitrator 210 implements a simple static priority-based arbitration mechanism.
AS FIG. 3 illustrates, the REQ1 line is turned ON and the REQ2 line is turned OFF simultaneously. When REQ1 is turned ON, arbitrator 210 activates the EN1 enable signal, which takes line driver 230A out of a high-impedance state and allows line driver 230A to write Data Bit 1 (DB1) from a first hardware source to Date Bit Line 1 of shared bus 240. When REQ2 is turned OFF, arbitrator 210 de-activates the EN2 enable signal, which puts line driver 230B into a high-impedance state and prevents line driver 230B from writing Data Bit 1 (DB1) from a second hardware source to Date Bit Line 1 of shared bus 240.
However, due to unequal propagation delays caused by inverter 215 and AND gate 220, the EN1 enable signal does not turn ON after or simultaneously with the EN2 enable signal turning OFF. As a result, the EN1 enable signal and the EN2 enable signal are both ON during the period T1 in FIG. 3. Line driver 230A is being driven by a data bit, DB1, equal to Logic 1 from a first hardware source. Line driver 230B is being driven by a data bit, DB1, equal to Logic 0 from a second hardware source. During the time period T1, line driver 230A tries to drive Data Bit Line 1 of shared bus 240 high at the same time that line driver 230B pulls Data Bit Line 1 of shared bus 240 low by sinking current. Thus, a short circuit current flows between tristate line drivers 230A and 230B during the time period T1, causing a large an unnecessary power dissipation. The faster shared bus 240 operates, the more often such short-circuits occur and the higher the power dissipation.
Therefore, there is a need in the art for an improved bus arbitrator that reduces the power consumption of a shared bus system. In particular, there is a need for a bus arbitrator that prevents short-circuits between tristate line drivers on a common address or data bus.